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  1. #1
    Membro Avatar de TeMpEsT
    Mar 2001

    Sobre as Latencias

    Alguem poderia me explicar como funcionam ?
    Tenho um A64, eu sei que quanto menos melhor, que se você subir elas um pouco dá pra subir o clock da memoria, e tudo mais..

    Mas eu queria entender como que cada uma funciona.. Alguem tem saco de explicar?

    E porque diabos meu DRAM Idle timer tá em 256? Será que posso baixar? Não é muito não?

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  3. #2
    Membro Avatar de V1P3R_BR4Z1L14N
    The cake is a lie
    Jul 2004

    dram idle em 256 é normal

    RAM Latency Explained

    When you buy RAM, you'll see two main speed ratings listed:
    frequency (the maximum rated clock rate), and latency. Memory speed is certainly important if you're considering overclocking, but for now we're concerned only with latency. Low latency memory, running at low latency settings, supposedly speeds up your system without requiring you to overclock it.
    Memory latency is almost always designated in one of two ways. It's either a single number denoting the CAS latency, or a string of four numbers denoting several latencies. CL=2.5, CAS=2.5, or C=2.5 would be common "single number" listings for RAM with a CAS latency of 2.5 cycles, for instance. A four-number designation would be something like 3-4-4-8, in which the four numbers relate to CAS – tRCD – tRP – tRAS. That's a lot of weird abbreviations, so here's the basics of what they mean:

    Column Access Strobe (sometimes Column Access Select). This is actually the last stage in finding where data is physically located in RAM. Data is stored in an array of columns and rows–the row is selected first, then the column is selected and the data in memory is either read from or written to. CAS is the amount of time, in cycles, between receiving the column access command and acting upon it. It is usually a value of 2, 2.5, or 3.

    RAS (Row Access Strobe) to CAS delay. This is the delay, in number of cycles, between finding the row of a location in memory, and finding the column. This value is usually between 3 and 5 cycles, but it doesn't tend to have a huge impact on performance. Sequential bits of data are usually stored along the same row in memory, so rows are not re-selected nearly as often as columns.

    RAS precharge. This is how much time it takes for the memory to stop accessing one row and start accessing another. Like tRCD, this value is typically between 3 and 5 cycles for modern memory systems. It can have an impact on performance when programs use large blocks of memory that span several rows.

    Active to Precharge Delay. This is the delay, in cycles, between the pins of the memory module electronically receiving a signal and the module starting the Row Access Strobe to locate and retrieve (or write) it. This is generally a pretty big delay, from 5 to 8 cycles on most DDR memories. But it also doesn't have a huge impact on performance, and should only make a big difference when memory access patterns change dramatically.
    That's probably all still a bit confusing, so here's the chronological sequence of events: First the pins receive a request to, let's say, retrieve memory at a certain address. The first latency measurement that comes into play is tRAS, as the memory waits to activate the row where the data resides. Then tRP comes into play if the requested data resides on a different row than the one previously accessed. After the row is selected (if necessary), you have the tRCD delay before the column is selected. Then CAS is the time it takes to select the proper column of memory and retrieve data stored there. To recap, listed chronologically, it's tRAS -> tRP -> tRCD -> CAS. And CAS has the biggest impact on performance, since new columns are accessed more frequently than anything else.

    basicamente é isso, mas dependendo da sua placa-mãe tem mto mais opçoes

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