RADEON 9800 PRO specification at the time of its announcements:
1. Fab process: 0.15 micron;
2. Transistors: 115 M;
3. Core clock speed: 380 MHz;
4. Memory bus: 256 bit DDR (DDR II will possibly be supported later);
5. Local memory size: up to 256 MB;
6. Memory clock speed: 340 DDR (680) MHz, 24 GB/s bandwidth;
7. Interface bus: AGP 8x, 2 GB/s bandwidth;
8. Full support of DX9's main features:
1. Floating-point 64 and 128 bit data formats for textures (including 3D and cubic textures) and frame buffer (vectors of 4 components of F16 or F32);
2. Pixel pipelines with floating-point arithmetics (F24 or F24[3+1] calculations);
3. Pixel Shaders 2.0;
4. 4 independent vertex pipelines;
5. Vertex Shaders 2.0;
6. N-Patches hardware tessellation with Displacement Mapping, and, if possible, adaptive detail level;
7. New F-buffer technology supports almost unlimited pixel shaders.
9. 8 independent pixel pipelines
10. 8 texture units (one for pixel pipeline) supporting trilinear filtering without speed loss and a combination of anisotropic and trilinear filtering.
11. 4-channel (4 64-bit channels) memory controller connected to the accelerator's core and AGP switch on the peer-to-peer basis;
12. HyperZ III+ memory optimization technology (Fast Z Clear and 8x8 depth buffer compression, Hierarchical Z Buffer for fast visibility checking);
13. Additional optimizations for speedy operation of the double-side stencil buffer.
14. Early Z test (pixel shaders work only for visible pixels);
15. Hardware acceleration of MPEG 1/2 unpacking and compression, VIDEOSHADER technology (arbitrary processing of a video flow with pixel shaders);
16. Two independent CRTC;
17. Two built-in 10bit 400 MHz RAMDAC with hardware gamma correction;
18. Integrated TV-Out;
19. Integrated DVI (TDMS transmitter) interface, up to 2043*1536.
20. Integrated general-purpose digital interface for external RAMDAC or DVI transmitter and for coupling with TV tuner.
21. FC packaging (FlipChip).